Sony HXC-100 Service Manual page 107
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Also See for HXC-100:
- Operating instructions manual (149 pages) ,
- Service manual (130 pages) ,
- Operating instructions manual (44 pages)
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007
DAYTONA-MAIN-RESET
003,007
OSC_27MHz
IC401
003
74M-CLK-DAYTONA-MAIN
+3.8V
NJM2871BF33-TE2
CL415
0.8
5
4
FB403
VIN
VOUT
C449
R428
C447
22k
10uF
1
3
0.1uF
CTL
N_BYP
6.3V
1608
FB404
10V
GND
3
C448
CE
0.1uF
2
10V
C438
10uF
GND
001,008
DAY_PLL33_P-ON-p
from DEMUX FPGA
007
DAYTONA-MAIN-GPIO
D401
1SS302-TE85L
1
(+2.5V)
R434
2
220
3
+2.5V
(+1.819V)
IC404
R1173H001D-T1-F
R435
R436
4
10k
22k
3
VDD
5
CE
VOUT
1
ADJ
GND
(1.0V)
C450
10uF
2
6.3V
HXC-100/V2 (J, E)
I
J
+3.2V
IC403 (2/2)
TC7SZ08FU(TE85R)
C446
VCC
0.1uF
GND
GND
R407
47
IC403 (1/2)
TC7SZ08FU(TE85R)
2
4
R408
47
1
CD-RESET_3
+3.2V
PLL/Test IF
R414
+3.2V
R413
10k
47
FB402
P2
C440
0.1uF
SYS_RESET_X
CL411
M1
1uF
PLL_BP0
C441
0.8
R406
10k
CL410
N2
X400
BP_CKSEL
0.8
27MHz
CL407
N3
4
GND
R411
BP_GCELL
0.8
VDD
22
CL403
P1
1
3
CONT
OUT
FORCEBYPASS
0.8
OE
GND
H1
R412
CLK_27M
2
22
R415
1k
N1
GND
CLK_27M_VCO
N6
GND
CLK_27M_DDR
R416
L4
47
EXT_PCLK
CL404
L3
L400
EXT_ACLK
1uH
0.8
R410
100
M3
PL0_AVD
C443
M2
IC402
0.1uF
L401
C442
PL0_AVS
R1173H001D-T1-F
1uH
4
47uF
N4
PL1_AVD
CL402
VDD
5
(+1.2V)
R409
0
C444
0.1uF
M4
L402
VOUT
PL1_AVS
1uH
R404
1k
1.2
C6
PL3_AVD
1
R405
C445
D6
1k
0.1uF
ADJ
PL3_AVS
GND
(1.0V)
C439
2
R403
CL405
W7
10uF
10k
PWM
0.8
CL409
U17
CHIP_TEST_MODE
0.8
CL406
U21
ARM_TESTEN
0.8
CL412
U22
ARM_INNOTEXTEST
0.8
CL408
V19
ARM_BISTOUT
0.8
R442
10k
Y8
FRSEL
R429
AA8
100
NM
FLASHSEL
GND
R441
10k
AB8
FFWRT
R430
100
U7
+3.2V
NM
HALTBOOTUP
R431
100
U19
NM
TIC_MODE
T4
AMI_TRST
T3
AMI_TDI
T2
AMI_TMS
T1
AMI_TCK
R4
AMI_RTCK
R3
AMI_TDO
(ENC=Lo)
R432
1k
L6
GPIO[0]
R433
100
K6
DAYTONA-MAIN-GPIO_1
GPIO[1]
R440
J6
DAYTONA-MAIN-GPIO_2
100
GPIO[2]
K4
GPIO[3]
K3
GPIO[4]
GND
K2
GPIO[5]
K1
GPIO[6]
J4
GPIO[7]
AA13
TEST_MON[0]
AB13
TEST_MON[1]
W12
TEST_MON[2]
Y12
TEST_MON[3]
AA12
TEST_MON[4]
AB12
TEST_MON[5]
U11
TEST_MON[6]
W11
TEST_MON[7]
Y11
TEST_MON[8]
AA11
TEST_MON[9]
AB11
TEST_MON[10]
W10
+1.8V-5
TEST_MON[11]
Y10
CL416
+1.8V-5
TEST_MON[12]
0.8
AA10
TEST_MON[13]
AB10
TEST_MON[14]
U9
TEST_MON[15]
R439
W8
1M
C451
C452
TEST_MDSEL[4]
10uF
10uF
W9
NM
TEST_MDSEL[0]
6.3V
6.3V
Y9
TEST_MDSEL[1]
AA9
TEST_MDSEL[2]
R437
AB9
10k
TEST_MDSEL[3]
IC400
R438
CXD9218GG
2.2k
GND
K
CD-61 (4/12)
CD-61 (4/12)
2.5V
from DPR
002,007,010
DAYTONA-MAIN-FVH
002
MAIN-A-Y/C
2.5V
DAYTONA-MAIN_F
DAYTONA-MAIN_V
+2.5V
DAYTONA-MAIN_H
3.2V
from DEMUX FPGA
007
DAYTONA-MAIN-FSYNC
MAIN-A_Y_0
GND
MAIN-A_Y_1
MAIN-A_Y_2
MAIN-A_Y_3
MAIN-A_Y_4
MAIN-A_Y_5
MAIN-A_Y_6
MAIN-A_Y_7
MAIN-A_Y_8
MAIN-A_Y_9
MAIN-A_C_0
GND
MAIN-A_C_1
MAIN-A_C_2
MAIN-A_C_3
MAIN-A_C_4
MAIN-A_C_5
MAIN-A_C_6
MAIN-A_C_7
MAIN-A_C_8
MAIN-A_C_9
(4/6)
3-7
3-7
L
M
CL413
0.8
Video/RTP Data IF
CL414
0.8
R427
A4
V20
10
R417 NM
47
NM
MCLC_CK
DTIF_PCLK
R418
100
D5
AA14
MCLC_FIELDID
DRIF_TX_RD_RDY2
R419
100
C5
AB14
MDTR_DHEN_TX
MCLC_VAL_V
DRIF_DHEN
R420
100
B5
U13
MDTR_DDEN_TX
MCLC_VAL_H
DRIF_DDEN
R421
1k
A5
V21
MCLC_VAL_DE
DTIF_PLD_REQ
R422
100
R423
1k
U20
W20
NM
FSYNC
DTIF_PLD_ST
NM
1k
V22
R424
DTIF_PLD_EN
NM
G4
Y13
R425
1k
1
2
MCLC_Y[0]
DRIF_PATHSEL0
G3
W13
R426
1k
RB401
3
4
MCLC_Y[1]
DRIF_PATHSEL1
100
5
6
G2
MCLC_Y[2]
GND
G1
W21
7
8
MDTR_DT_TX_0
MCLC_Y[3]
DTIF_DATA[0]
F4
W22
1
2
MDTR_DT_TX_1
MCLC_Y[4]
DTIF_DATA[1]
RB402
3
4
F3
Y21
MDTR_DT_TX_2
MCLC_Y[5]
DTIF_DATA[2]
100
5
6
F2
Y22
MDTR_DT_TX_3
MCLC_Y[6]
DTIF_DATA[3]
F1
AA22
7
8
MDTR_DT_TX_4
MCLC_Y[7]
DTIF_DATA[4]
E4
AB21
1
2
MDTR_DT_TX_5
MCLC_Y[8]
DTIF_DATA[5]
RB403
3
4
E3
Y20
MDTR_DT_TX_6
MCLC_Y[9]
DTIF_DATA[6]
100
E2
AA20
5
6
MDTR_DT_TX_7
MCLC_Y[10]
DTIF_DATA[7]
E1
AB20
7
8
MDTR_DT_TX_8
MCLC_Y[11]
DTIF_DATA[8]
W19
MDTR_DT_TX_9
DTIF_DATA[9]
1
2
D4
Y19
MDTR_DT_TX_10
MCLC_C[0]
DTIF_DATA[10]
RB404
D3
AA19
3
4
MDTR_DT_TX_11
MCLC_C[1]
DTIF_DATA[11]
100
D2
AB19
5
6
MDTR_DT_TX_12
MCLC_C[2]
DTIF_DATA[12]
7
8
D1
W18
MDTR_DT_TX_13
MCLC_C[3]
DTIF_DATA[13]
C3
Y18
7
8
MDTR_DT_TX_14
MCLC_C[4]
DTIF_DATA[14]
RB405
C2
AA18
5
6
MDTR_DT_TX_15
MCLC_C[5]
DTIF_DATA[15]
100
C1
AB18
3
4
MDTR_DT_TX_16
MCLC_C[6]
DTIF_DATA[16]
1
2
B1
W17
MDTR_DT_TX_17
MCLC_C[7]
DTIF_DATA[17]
B3
Y17
7
8
MDTR_DT_TX_18
MCLC_C[8]
DTIF_DATA[18]
RB406
A3
AA17
5
6
MDTR_DT_TX_19
MCLC_C[9]
DTIF_DATA[19]
100
3
4
C4
AB17
MDTR_DT_TX_20
MCLC_C[10]
DTIF_DATA[20]
1
2
B4
W16
MDTR_DT_TX_21
MCLC_C[11]
DTIF_DATA[21]
Y16
MDTR_DT_TX_22
DTIF_DATA[22]
H3
AA16
MDTR_DT_TX_23
MCIS_LRCK
DTIF_DATA[23]
H2
AB16
MDTR_DT_TX_24
MCIS_BCK
DTIF_DATA[24]
J3
U15
MDTR_DT_TX_25
MCIS_CH12
DTIF_DATA[25]
J2
W15
MDTR_DT_TX_26
MCIS_CH34
DTIF_DATA[26]
J1
Y15
MDTR_DT_TX_27
MCIS_CH56
DTIF_DATA[27]
H4
AA15
MDTR_DT_TX_28
MCIS_CH78
DTIF_DATA[28]
AB15
MDTR_DT_TX_29
DTIF_DATA[29]
W14
MDTR_DT_TX_30
DTIF_DATA[30]
Y14
MDTR_DT_TX_31
DTIF_DATA[31]
IC400
(1/6)
CXD9218GG
N
O
1
to CAFE-T
MDTR_TX
006
2
3
4
CD-61 (4/12)
BOARD NO. 1-879-612-11
HSC-300_CD-61_011_4
5
P
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