Cisco ASR 9000 Series Configuration Manual page 31
Configuring clear channel t3/e3 and
channelized t3 and t1/e1 controllers on the
cisco asr 9000 series router
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Also See for ASR 9000 Series:
- Command reference manual (1138 pages) ,
- Routing configuration manual (702 pages) ,
- Reference manual (696 pages)
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Configuring Clear Channel T3/E3 and Channelized T3 and T1/E1 Controllers on the Cisco ASR 9000 Series Router
BERT is data intrusive. Regular data cannot flow on a line while the test is in progress. The line is put
in an alarm state when BERT is in progress and restored to a normal state after BERT has been
terminated.
Configuring BERT on T3/E3 and T1/E1 Controllers
This task explains how to enable a bit error rate test (BERT) pattern on a T3/E3 or T1/E1 line or an
individual channel group.
Prerequisites
You must have configured a clear channel T3/E3 controller, or a channelized T3-to-T1/E1 controller.
Restrictions
Before configuring BERT on the 1-Port Channelized OC-48/STM-16 SPA, consider the following
restrictions:
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Before configuring BERT on the 4-Port Channelized T3/DS0 SPA, consider the following restrictions:
•
•
•
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These test patterns are supported on the 8-Port Channelized T1/E1 SPA for T1/E1/DS0:
OL-32684-01
Only two simultaneous BERT tests are possible per STS-12 stream.
These test patterns are supported:
2^15-1 (O.151)
–
2^20-1 (O.151) - QRSS
–
2^23-1 (O.151)
–
Fixed Patterns (all 0s, all 1s etc.)
–
–
Single bit error injection
–
Data inversion
A maximum of 12 BERT sessions is supported.
6 simultaneous BERT sessions among the first three physical ports and 6 simultaneous BERT
sessions on the fourth port are supported.
Only one BERT session per T1 is supported.
These test patterns are supported on the 4-Port Channelized T3/DS0 SPA:
2^11-1—T1/E1/DS0 only
–
2^15-1 (O.151)
–
2^20-1 (O.153)—T3 only
–
2^20-1 (QRSS)
–
2^23-1 (O.151)
–
Alternating 0s/1s
–
Fixed Patterns (all 0s, all 1s etc.)
–
1 in 8 DS1 insertion—T1/E1/DS0 only
–
–
3 in 24 DS1 insertion—T1/E1/DS0 only
Cisco ASR 9000 Aggregation Services Router Interface and Hardware Component Configuration Guide
How to Configure Clear Channel T3/E3 Controllers and Channelized T1/E1 Controllers
475
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