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FO-4500H
LH28F800SUT (IC6) Terminal descriptions
Symbol
A0
A
- A
1
15
A
- A
16
20
DQ
- DQ
0
7
DQ
- DQ
8
15
CE
#, CE
#
0
1
RP#
OE#
WE#
RY/BY#
WP#
BYTE#
3/5#
Vpp
Vcc
GND
NC
3/5#
CE1#
NC
A20
A19
A18
A17
A16
Vcc
A15
A14
A13
A12
CE0#
Vpp
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
Type
Byte select address: The device selects the low-order or high-order byte in the ×8 mode. Not
I
used in the ×16 mode.
(The A
input circuit is not activated since Byte # is high.)
0
I
Word select address: One word is selected in the 64 KByte block.
These addresses are latched in the data writing operation.
I
Block select address: 1/32 erasion block is selected. These addresses are latched when data
writing, erasion or lock block is activated.
I/O
Low-order byte data input/output: Data and command input in the command user interface
writing cycle. When various data are read, the memory array, page buffer, identifier and status
data are output. It is floated when the chip is not selected or output is disable.
I/O
High-order byte data input/output: Same function as the low-order byte data input/output.
Operable in the ×16 mode alone. It is floated in the ×8 mode.
I
Chip enable: The control logic, input butter, decoder and sense amplifier are made to be active.
The chip is active only when both CE
I
Reset/power down: The device is brought into the deep power down state when RP# is turned to
"Low". In order to recover it from the deep power down state, 400ns (ordinary lead time of +5ns
for reading) is necessary. When RP# pin becomes "low", all chip operations are interrupted and
reset.
I
Output enable: Data is output from DQ pin by turning OE# to "Low". When OE# is turned to
"High", DQ pin is floated.
I
Write enable: The accesses to the command user interface, buffer, data cue register and
address cue latch are controlled. When WE# is "Low", it becomes active to fetch the address and
data at the leading edge.
O
Ready/busy: The status of the internal write state machine is output. "Low" indicates that the
write state machine is in operation. RY/BY# pin is floated when the write state machine waits for
instruction of next operation, erasion is interrupted or it is in the deep power down state.
I
Write protect: Each block can be protected from writing/erasion by writing data into the no-volatile
lock bit of the block. Writing/erasion becomes impossible for the block in which WP# is "low" and
the block lock status bit (BSR.6) is protected. If WP# is "High", writing/erasion is possible
regardless of the status of the lock bit. When RP# is "low" (in the deep power down state), WP#
input circuit becomes disable.
Byte enable: When BYTE# is turned to "Low", the device is brought into the ×8 mode. At this
I
time, DQ8-DQ15 becomes floated. The address A0 selects the high-/low-order byte. When
BYTE# is "High", the device is brought into the ×16 mode, and the A0 input circuit becomes
disable.
I
3.3V/5.0V: When 3/5# is "High", the internal circuit can be operated at 3.3V, and when 3/5# is
"Low", the internal circuit can be operated at 5.0V.
* Note: If 3/5# is turned to "High" when 5V is applied to Vcc, the device may be broken.
Writing/erasion power: 5.0±0.5V is applied during writing/erasion.
Device power: 5.0±0.5V or 3.3±0.3V
Ground
Not connected.
1
2
3
4
5
6
7
8
9
10
11
12
13
56-LEAD TSOP PINOUT
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name and function
# and CE
0
LH28F800SUT
14mm x 20mm
TOP VIEW
5 – 16
# are at "low".
1
WP#
56
WE#
55
OE#
54
RY/BY#
53
DQ15
52
DQ7
51
DQ14
50
DQ6
49
GND
48
DQ13
47
DQ5
46
DQ12
45
DQ4
44
Vcc
43
GND
42
DQ11
41
DQ3
40
DQ10
39
DQ2
38
Vcc
37
36 DQ9
35 DQ1
34 DQ8
33 DQ0
32 A0
31 BYTE#
30 NC
29 NC
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