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• IC Pin Function Description
CD BOARD IC101 TC94A70FG-101 (CD-MP3 PROCESSOR)
Pin No.
Pin Name
1
2
3
4
SBAD/RFDC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
IO0 (/HSO)
21
IO1 (/UHSO)
22
23
24
TE
L 13942296513
25
26
27
28
29
30
31
32
33
34
35
36
SRAMSTB
37
38, 39
BUS0, BUS1
40
BUS2 (SO)
41
BUS3 (SI)
42
BUCK (CLK)
43
44
45
46
AoUT3 (PO4)
47
AoUT2 (PO5)
48
49
www
50
51
52
.
53
54
55
SBOK/FOK
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I/O
AVSS3
-
Ground terminal
RFZi
I
RF ripple zero crossing signal input terminal
RFRP
O
RF ripple signal output terminal
O
Sub beam addition signal or RF peak detection signal output terminal
FEi
O
Focus error signal output terminal
TEi
O
Tracking error signal output terminal
TEZi
I
Tracking error zero crossing signal input terminal
AVDD3
-
Power supply terminal (+3.3 V)
FOo
O
Focus coil drive signal output terminal
TRo
O
Tracking coil drive signal output terminal
VREF
I
Reference voltage (+1.65V) input terminal
FMO
O
Sled motor drive signal output terminal
DMO
O
Spindle motor drive signal output terminal
VSSP3
-
Ground terminal
VCOi
I
VCO control voltage input terminal
VDDP3
-
Power supply terminal (+3.3 V)
VDD1
-
Power supply terminal (+1.5 V)
VSS1
-
Ground terminal
FGiN
I
FG signal input terminal
I
Disc inner position detection signal input terminal
O
Not used
XVSS3
-
Ground terminal
XI
I
System clock input terminal (16.9344 MHz)
XO
O
System clock output terminal (16.9344 MHz)
XVDD3
-
Power supply terminal (+3.3 V)
DVSS3
-
Ground terminal
RO
O
Analog audio (R-ch) signal output terminal
DVDD3
-
Power supply terminal (+3.3 V)
DVR
O
Reference voltage (+1.65V) output terminal
LO
O
Analog audio (L-ch) signal output terminal
DVSS3
-
Ground terminal
VDDT3
-
Power supply terminal (+3.3 V)
VSS1
-
Ground terminal
VDD1
-
Power supply terminal (+1.5 V)
VDDM1
-
Power supply terminal (+1.5 V)
I
S-RAM standby mode control signal input terminal
XRST
I
Reset signal input from the system controller
I
Serial data input from the system controller or USB controller
I
Serial data input from the system controller or USB controller
I
Serial data input from the system controller or USB controller
I
Serial data transfer clock signal input from the system controller or USB controller
XCCE
I
Chip enable signal input from the system controller or USB controller
TEST
I
Setting terminal for test mode
IRQ
I
Interrupt request signal input terminal
O
Clock siganl output to the A/D converter
O
Audio data output to the USB controller
PIO0
O
Request signal output to the system controller or USB controller
PIO1
O
Request signal output to the USB controller
PIO2
O
Data selection signal output to the data selector/reset signal output to the A/D converter
x
ao
PIO3
I
Gate signal input from the USB controller
y
VSS1
-
Ground terminal
i
VDDT3
-
Power supply terminal (+3.3 V)
SBSY
O
Subcode block sync signal output to the system controller
O
Not used
http://www.xiaoyu163.com
HCD-GT111/GT222/GT444/GT555
8
Not used
Not used
Q Q
3
6 7
1 3
Normally fi xed at "L"
u163
.
2 9
9 4
2 8
Description
Not used
1 5
0 5
8
2 9
9 4
Fixed at "L" in this set
"L": reset
m
co
9 9
2 8
9 9
57