Baseband Electrical (Digital); Pog (U1000); Graphics Accelerator - Motorola V975 Service Manual
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Service Manual(Level 3)
Baseband Electrical (Digital)
POG (U1000)
POG is the baseband processor IC of the 3G chipset
solution. POG is crafted to provide a high performance
embedded solution at low power for 3G mobile de-
vices. POG is a TriCore processor IC integrating a pow-
erful DSP core, a 32bit MCU RISC core with unified
cache and a custom 32bit RISC engine for data move-
ment across the processing domains.
Figure 3-18. POG Block Diagram
VIDEO SAP
USB
UART3
(VSAP)
StarCore
Platform
DMA 2
Q2IP
SRAM
QMDA
(8)
WCSP
EBIF
MDI
Serial
BBP
Debug
Timer
L1T_1/2
Watchdog
MQSPI
Audio
SAP
POG
GPIO
(U1000)
1 & 2
Not used in this design
The DSP core is a high performance StarCore with four
parallel ALUs, the SC140, with a novel Variable Length
Execution Set (VLES) architecture which maximizes the
execution of multiple instructions in a single clock cycle.
The SC140 is assisted by 3G specific hardware accel-
erators and timers to optimize performance and power.
As part of the 3G support, the Wideband CDMA Sig-
nal Processor (WCSP) module implements modem
functions required by the CDMA subscriber unit in ac-
Draft 1.0
UART1
UART2
MMC
RS232/IrDa
RS232/IrDa
GPIO
3 & 4
Keypad
IPCM
Platform
M*Core
Watchdog
Platform
One Wire
SIM _1/2
SGPT
GQSPI
2 Clk Mon
Clk Control
2 PLLs
EIM
SDRAM Ctl.
GEM
HACC
LCD SRAM
LCD
Controller
Video
Buffer
Motorola Confidential Proprietary
Baseband Electrical (Digital)
cordance with the 3GPP specifications.
The 32bit MCU RISC core is the M*Core M341 de-
signed for high performance and low power embedded
systems. The M341 embodies an 16K unified cache,
integer multiplier and MMU in support of virtual memory
management OSes.
Data communication across the cores is handled by a
flexible 32bit RISC machine, the Inter Processor Com-
munication Module (IPCM). The IPCM supports flex-
ible data flow between the MCU, DSP and the multi-
media peripherals.
Graphics Accelerator
U5201 is a high performance, low power, Graphics/
Media Processor IC (GPU) that supports advanced
multimedia applications for W-CDMA, UMTS, and
GSM. This IC enables the user to capture, view, and
share high quality images and video. A hardware-based
Figure 3-19. GPU Interface
GPU_INTb
PCAP_RESETb
DATA(15:0)
GPU_IND_ADDR
POG
(U1000)
MPEG-4 encoder captures video at up to CIF resolu-
tion at 30fps. A hardware-based video decoder allows
playback of the video recorded, or any other MPEG-4
clip or streaming video. A full hardware codec is uti-
Theory of Operation
Graphics
Accelerator
(U5201)
J7500
J7900
Main
VGA
CIF
Display
Cam
Cam
3-15
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