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5-7. TUNER/TIMER CONTROL MICROPROCESSOR PIN FUNCTIONS
(MA-360 BOARD IC460)
Pin No.
Pin Name
I/O
1
SYNC ON
O
2
POWER FAIL
I
3
H DET
I
4
SIRCS IN
I
5
STEREO DET
I
6
SW1 SIRCS OUT
O
7
BUZZER
O
8
N.C
9
ARC_LED
O
10
SCK 0
I
SI 0
11
I
SO 0
12
O
13
EEP WP
O
14
LANC IN
I
15
LANC OUT
O
16
A/D 0
I
17
A/D 1
I
18
A/D 2
I
19
A/D 3
I
20
A/D 4
I
21
ML LED
O
22
X CS
O
23
AFT
I
24
AVDD
I
25
AV REF
26
SCL 0
O
27
CG CS
O
28
SDA 0
O
29
JOG LED
O
30
AVSS
I
31
EXTAL
32
XTAL
33
VSS
I
34
RST
I
35
PLL CLK
O
36
PLL DATA
O
37
PLL ENABLE
O
38
MAIN/SAP
O
39
SAP DET
I
40
V SET CS
O
41
DMS 1
I
42
DMS 2
I
43
VFDP
I
44
SEG1
O
45
SEG2
O
46
SEG3
O
47
SEG4
O
48
SEG5
O
49
SEG6
O
50
SEG7
O
Function
During Laser Link signal resived "H".
Power failure detect signal input.
H DET_(Tuner Hsync detect input).
Remote control signal input.
Stereo judge input.
Remote control signal output.
Buzzer signal output.
Not used.
ARC led control "H" when ARC on.
Serial communication signal (clock).
Serial communication signal
(data in).
Serial communication signal
(data out).
EEP mode control.
LANC input.
LANC output.
Analog voltage (key) input.
Analog voltage (key) input.
Analog voltage (key) Input.
Analog voltage (key) Input.
Analog voltage (key) Input.
ML LED ON/OFF control.
Memory label board chip select
signal out.
Auto fine tuning signal input.
A/D port reference input.
UNSW 5 V.
T BUS (clock) /IIC BUS (clock).
Character generator chip select
signal.
IIC BUS (data).
JOG LED control signal output.
Ground.
System clock terminal (16 MHz).
System clock terminal (16 MHz).
Ground.
RESET input.
TUNER PLL clock.
TUNER PLL data.
TUNER chip select.
Main/SAP judge signal output.
Main/SAP judge signal input.
Vset IC chip select signal.
DMS forward/reverse signal input.
DMS forward/reverse signal input.
VFDP.
Segment terminal 1
Segment terminal 2
Segment terminal 3
Segment terminal 4
Segment terminal 5
Segment terminal 6
Segment terminal 7
Pin No.
Pin Name
51
SEG8
52
SEG9
53
SEG10
54
SEG11
55
SEG12
56
SEG13
57
SEG14
58
SEG15
59
SEG16
60
N.C
61
N.C
62
GRID10
63
GRID9
64
GRID8
65
GRID7
66
GRID6
67
GRID5
68
GRID4
69
GRID3
70
GRID2
71
GRID1
72
VDD
73
TX
74
TEX
75
NC/VCC
76
ASURA CS
77
SYS RESET
78
POWER CONT M12
79
POWER CONT SW12
80
CG V
5-4E
I/O
Function
O
Segment terminal 8.
O
Segment terminal 9.
O
Segment terminal 10.
O
Segment terminal 11.
O
Segment terminal 12.
O
Segment terminal 13.
O
Segment terminal 14.
O
Segment terminal 15.
O
Segment terminal 16.
Not used.
Not used.
O
Grid terminal 10.
O
Grid terminal 9.
O
Grid terminal 8.
O
Grid terminal 7.
O
Grid terminal 6.
O
Grid terminal 5.
O
Grid terminal 4.
O
Grid terminal 3.
O
Grid terminal 2.
O
Grid terminal 1.
I
D5 V
Timer clock terminal (32.768 kHz).
Timer clock terminal (32.768 kHz).
O
D5 V
S/S microcomputer chip select
O
signal.
O
System reset output.
O
Power supply control signal.
O
Power supply control signal.
I
Composite sync input.
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